1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to an improvement of a redundancy decoder portion thereof.
2. Description of the Related Art
In a prior art semiconductor memory device including a plurality of memory cell blocks, two redundancy memory cell rows (or columns) are incorporated into each of the memory cell blocks. In this case, two redundancy decoders are provided for each of the memory cell blocks. In other words, the number of redundancy decoders is twice that of memory cell blocks. Therefore, when two defectice memory cells are found in one of the memory cell blocks, addresses (hereinafter, referred to as defective addresses) of the cells are written into the redundancy decoders of the same memory cell block by laser trimming or the like. As a result, when one of the defective addresses is received by its corresponding redundancy decoder the redundancy decoder deactivates the normal memory cells of the same memory cell block and in its place, selects the corresponding redundancy memory cell row (or column). Thus, the defective memory cell is replaced by a redundancy memory cell, and alleviated. This will be explained later in detail.
In the above-described prior art semiconductor memory device, however, since the number of redundancy decoders is too large, the integration of the device is low.